1. Technical Field of the Invention
This disclosure relates to a semiconductor integrated circuit device and in particular to a semiconductor memory device.
2. Description of the Related Art
Various procedures including designing, processing, packing, and testing are required to make semiconductor integrated circuits. In addition, the testing is classified into function, parameter, and burn-in methods. In these methods, semiconductor integrated circuits may be tested at a wafer, die, or package level. Although packing was a relatively cheap procedure, semiconductor makers packaged devices before testing (or before appropriate operations of a semiconductor integrated circuit device were secured). But, in connection with the fact that the structure of semiconductor integrated circuit devices is becoming increasingly complicated, the testing of semiconductor integrated circuit devices is required at a wafer or die level in order to reduce possibility of packing abnormal semiconductor integrated circuit devices.
As in packing procedures, control, address and data pins are necessary for accessing a semiconductor memory device at a wafer level. Memory cells are accessed by proper row and column addresses. This addressing method is hereinafter referred to as “an absolute addressing method”. This addressing method requires not only the control and the data pins but also all the address pins, even at testing of package and wafer levels.
As an integration degree of semiconductor memory devices increase, the required test time increases in proportion to the integration degree. Increases in test time leads to increased fabrication costs and decreased productivity. Thus, it is desirable to reduce the required test time. In general, there are several ways to shorten the required test time at a wafer state.
One method is to reduce the testing time, which increases the number of semiconductor memory devices under test per unit time. This method causes a quality problem due to under-screening.
A second method is to reduce the number of semiconductor memory devices under test per a unit time by increasing the number of semiconductor memory devices that are tested at the same time. This method is greatly dependent upon the performance of a tester.
Still another method is to improve a process, which is a managing or systematic problem rather than a technical problem.
A basic limitation to the second method is that the number of channels of a tester is fixed. In general, for example, a tester provides 50 channels to test one memory device. As described above, writing/reading data in/from a memory (e.g., DRAM) at a wafer level is made using 5 control pins (e.g., CKE, CLK, /RAS, /CAS, /WE), 15 address pins (e.g., A0-A12, BA0-BA1) and 8/16 data pins (e.g., DQ0-DQ7 or DQ0-DQ15). That is, about 28 to 36 pins are used to test a memory device at a wafer level. Consequently, only one memory device may be tested using a tester that provides 50 channels, leaving 14 to 22 pins unused.
To test more semiconductor devices at the same time using the same tester, a way to test all the devices using a reduced number of address pins is needed. Embodiments of the invention address these and other limitations of the conventional art.